Jitter in integrated circuits has existed for a long time. Shrinking process technologies and increased clock speeds have brought this issue to the forefront. New designs attempt to balance jitter performance, speed, and design complexity, but as designs try to push speed and functionality performance boundaries, jitter performance is becoming a limiting factor.
In general, circuit designs includes clock(s), inputs, and generates outputs. Current and future circuit designs require higher input clock frequencies, and increased functionality for improved throughput. As speed and functionality increase, switching noise will proportionally increases. The switching noise from all the functional activities performed on clock edges will translate into increased jitter on at least one output of the circuit design. The increased jitter can negatively affect design performance. The negative effects range from degradation in IC performance to a total system failure.
Therefore, it is desirable to provide methods and circuits to manage output jitter of an IC. It is further desirable to provide methods to reduce jitter during the design phase of an IC.